A known analog to digital converter uses charge redistribution in a binary-weighted capacitor array to digitally encode analog signals. A sample of the analog signal is applied to a signal node to charge capacitors of the capacitor array, and a reference voltage is selectively applied to individual capacitors of the array to redistribute charge within the array until the voltage at the signal node is minimized. The pattern of reference voltages that is applied to the individual capacitors of the array to minimize the voltage at the signal node determines the bit pattern for the digitally encoded sample of the analog signal.
When such known analog-to-digital converters are implemented as part of a monolithic integrated circuit, other signals may be capacitively coupled to the signal node of the capacitor array. Such capacitive coupling causes a voltage offset at the signal node, and this voltage offset effectively shifts the decision levels for the digital encoding process away from their intended values, causing bit errors in the digitally encoded signal.
For example, the sign bit of the digitally encoded signal may be present in the integrated circuit near the signal node of the capacitor array and may be coupled to the signal node via parasitic capacitances. In known circuits, the sign bit has been inverted and integrated over time, and the integrated signal has been applied to the signal node to compensate for voltage offset due to parasitic coupling of the sign bit to the signal node. This approach averages out encoding errors over time, but particular bits of the encoded signal are still in error.